Difference between revisions of "Notes:RealQ Architecture/1-Byte operations"
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(Created page with "{| class="wikitable" border="1" |- ! Operation ! colspan="8" | bits ! Comment ! Caveats |- | {{C|LOAD r1,r2}} | colspan="2" | {{C|00}} | cols...") |
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Revision as of 19:19, 2 October 2015
| Operation | bits | Comment | Caveats | |||||||
|---|---|---|---|---|---|---|---|---|---|---|
| LOAD r1,r2 | 00 | r1 | r2 | sr2 | r1 must be 16bit, sr2=11 is unused. | |||||
| MOV r1,r2 | 01 | r1 | r2 | sr | registers must have same size-code[N 1] | |||||
| 01 | xx | xx | 11 | (see: SWP) | ||||||
Opcode notes
- ↑ That is must both be 16bit, low or high
