Difference between revisions of "Notes:RealQ Architecture/1-Byte operations"

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(Created page with "{| class="wikitable" border="1" |- ! Operation ! colspan="8" | bits ! Comment ! Caveats |- | {{C|LOAD r1,r2}} | colspan="2" | {{C|00}} | cols...")
 
 
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| {{C|[[Notes:RealQ instruction LOAD|LOAD]] r1,r2}}
 
| {{C|[[Notes:RealQ instruction LOAD|LOAD]] r1,r2}}
 
| colspan="2" | {{C|00}}
 
| colspan="2" | {{C|00}}
 +
| colspan="2" | {{C|sr2}}
 
| colspan="2" | {{C|r1}}
 
| colspan="2" | {{C|r1}}
 
| colspan="2" | {{C|r2}}
 
| colspan="2" | {{C|r2}}
−
| colspan="2" | {{C|sr2}}
+
| {{C|r1}} '''must''' be 16bit, {{C|1=sr2=11}} is unused
−
| {{C|r1}} '''must''' be 16bit, {{C|1=sr2=11}} is unused.
+
 
|
 
|
 +
|-
 +
| ''(Unused)''
 +
| colspan="2" | {{C|00}}
 +
| colspan="2" | {{C|11}}
 +
| colspan="2" | {{C|xx}}
 +
| colspan="2" | {{C|xx}}
 
|-
 
|-
 
| {{C|[[Notes:RealQ instruction MOV|MOV]] r1,r2}}
 
| {{C|[[Notes:RealQ instruction MOV|MOV]] r1,r2}}
 
| colspan="2" | {{C|01}}
 
| colspan="2" | {{C|01}}
 +
| colspan="2" | {{C|sr}}
 
| colspan="2" | {{C|r1}}
 
| colspan="2" | {{C|r1}}
 
| colspan="2" | {{C|r2}}
 
| colspan="2" | {{C|r2}}
−
| colspan="2" | {{C|sr}}
 
 
|
 
|
 
| registers must have same size-code<ref group="N">That is must both be 16bit, low or high</ref>
 
| registers must have same size-code<ref group="N">That is must both be 16bit, low or high</ref>
 
|-
 
|-
−
|  
+
| {{C|[[Notes:RealQ instruction SWP|SWP]] r}}
 
| colspan="2" | {{C|01}}
 
| colspan="2" | {{C|01}}
−
| colspan="2" | {{C|xx}}
 
−
| colspan="2" | {{C|xx}}
 
 
| colspan="2" | {{C|11}}
 
| colspan="2" | {{C|11}}
−
| colspan="2" style="text-align:center;" | ''(see: {{C|SWP}})''
+
| colspan="2" | {{C|00}}
 +
| colspan="2" | {{C|rr}}
 +
|-
 +
| {{C|[[Notes:RealQ instruction INC|INC]]}}
 +
| colspan="2" | {{C|01}}
 +
| colspan="2" | {{C|11}}
 +
| colspan="2" | {{C|01}}
 +
| colspan="2" | {{C|00}}
 +
| Only affects the {{C|A}} register
 +
|
 +
|-
 +
| {{C|[[Notes:RealQ instruction INC2|INC2]]}}
 +
| colspan="2" | {{C|01}}
 +
| colspan="2" | {{C|11}}
 +
| colspan="2" | {{C|01}}
 +
| colspan="2" | {{C|01}}
 +
| Only affects the {{C|A}} register
 +
|
 +
|-
 +
| {{C|[[Notes:RealQ instruction DEC|DEC]]}}
 +
| colspan="2" | {{C|01}}
 +
| colspan="2" | {{C|11}}
 +
| colspan="2" | {{C|01}}
 +
| colspan="2" | {{C|10}}
 +
| Only affects the {{C|A}} register
 +
|
 +
|-
 +
| {{C|[[Notes:RealQ instruction DEC2|DEC2]]}}
 +
| colspan="2" | {{C|01}}
 +
| colspan="2" | {{C|11}}
 +
| colspan="2" | {{C|01}}
 +
| colspan="2" | {{C|11}}
 +
| Only affects the {{C|A}} register
 +
|
 +
|-
 +
| ''(Unused)''
 +
| colspan="2" | {{C|01}}
 +
| colspan="2" | {{C|11}}
 +
| {{C|1}}
 +
| {{C|x}}
 +
| colspan="2" | {{C|xx}}
 
|}
 
|}
  

Latest revision as of 20:26, 2 October 2015

Operation bits Comment Caveats
LOAD r1,r2 00 sr2 r1 r2 r1 must be 16bit, sr2=11 is unused
(Unused) 00 11 xx xx
MOV r1,r2 01 sr r1 r2 registers must have same size-code[N 1]
SWP r 01 11 00 rr
INC 01 11 01 00 Only affects the A register
INC2 01 11 01 01 Only affects the A register
DEC 01 11 01 10 Only affects the A register
DEC2 01 11 01 11 Only affects the A register
(Unused) 01 11 1 x xx


Opcode notes

  1. ↑ That is must both be 16bit, low or high
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