Difference between revisions of "Notes:RealQ Architecture/1-Byte operations"
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| colspan="2" | {{C|xx}} | | colspan="2" | {{C|xx}} | ||
| colspan="2" style="text-align:center;" | ''(see: {{C|SWP}})'' | | colspan="2" style="text-align:center;" | ''(see: {{C|SWP}})'' | ||
| + | | | ||
| + | |- | ||
| + | | ''(Unused)'' | ||
| + | | colspan="2" | {{C|01}} | ||
| + | | colspan="2" | {{C|11}} | ||
| + | | colspan="2" | {{C|1x}} | ||
| + | | colspan="2" | {{C|xx}} | ||
|} | |} | ||
Revision as of 19:56, 2 October 2015
| Operation | bits | Comment | Caveats | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| LOAD r1,r2 | 00 | sr2 | r1 | r2 | r1 must be 16bit, sr2=11 is unused. | ||||||
| (Unused) | 00 | 11 | xx | xx | |||||||
| MOV r1,r2 | 01 | sr | r1 | r2 | registers must have same size-code[N 1] | ||||||
| 01 | 11 | xx | xx | (see: SWP) | |||||||
| (Unused) | 01 | 11 | 1x | xx | |||||||
Opcode notes
- ↑ That is must both be 16bit, low or high
